In current wireless communication networks, software-defined radio (SDR) devices may be implemented. SDR devices use reconfigurable hardware that may be programmed over the air to operate under different wireless protocols. For example, an SDR transceiver in a wireless laptop computer may be configured by a first software load to operate in a CDMA2000 wireless network and may be reconfigured by a second software load to operate in an HSDPA wireless network. SDR systems minimize cost (design time, TTM) and power consumption, while maximizing flexibility, thereby providing an optimized combination of scalability and modularity.
One such approach involves a re-configurable correlation unit that may be implemented in a context-based operation reconfigurable instruction set processor, as disclosed in U.S. patent application Ser. No. 11/501,577, incorporated by reference above. Such a correlation unit matches the architecture to the domain of application and optimizes the performance and power jointly. Thus, the real-time processing requirements and low-power requirements of wireless mobile stations are met simultaneously. The correlation unit is highly re-configurable and may be used for different functional blocks operating under different standards.
In these correlation units and other types of systems, including WCDMA and/or other pseudo-noise generating systems, scrambling code is widely used. In a WCDMA system, for example, the scrambling code sequences are constructed by combining two real sequences into a complex sequence. Each of the two real sequences is constructed as position wise modulo 2 sum of 38400 chip segments of two binary m-sequences. At the receiver side, the same scrambling code is generated and used to descramble the received signal.
Because the descrambling rate is high for a conventional WCDMA system, scrambling codes have to be processed at a high rate that forces the scrambling code generator either to run faster or to use parallel execution to make the descrambling processing faster. For example, for 4× parallelism, conventional systems provide for allowing the scrambling code generator to run four times faster, which increases the power consumption, or provide for duplication of the scrambling code generator four times, resulting in the consumption of at least four times more area. Other solutions use memory to store pre-calculated scrambling codes, which increases the memory usage and results in higher power consumption and increased die area. Furthermore, this solution makes support for changes in the scrambling code, such as during handover, difficult. Therefore, there is a need in the art for an improved method for generating codes.